Modern avionic systems on commercial aircraft typically transmit data from the cockpit to various flight surface controls, such as the stabilizer/trim rudder ratio changer module, yaw damper, and flap control unit, over a serial data bus. To minimize errors, a serial data format using different voltage levels on two conductors, described in Aeronautical Radio Incorporated (ARINC) Specification 429, has been developed for communication within and between avionic systems.
Integrated circuits that interface to an ARINC Specification 429 bus, i.e., to transmit and receive data, are already commercially available. For example, a Harris Model HS-3282 CMOS ARINC bus interface circuit includes dual receivers and a single transmitter section, and provides selectable data rates of either 12.5 kilobits per second or 100 kilobits per second, selectable word lengths of 25 or 32 bits, and an eight word first-in-first-out storage buffer. The small storage buffer on the Harris integrated circuit (IC) limits the amount of data that can be consecutively downloaded for transmission. Furthermore, due to the nonstandard word length it uses, the device cannot be easily interfaced directly to commonly available 8 and 16 bit microprocessors. Although the transmitter on the Harris chip can generate an internal self test signal that is input to both receiver sections, the self test is limited to detecting faults in the two receiver sections and cannot test for proper operation of the transmitter section, nor can it determine whether a fault exists in data input to the chip.
Accordingly, it is an object of the present invention to provide a serial data bus transmitter that includes a substantially greater storage buffer than presently provided on commercially available devices, enabling the transmitter to be addressed by an external microprocessor as if it were a memory location. A further object is to provide dual transmitters on a single integrated circuit. Yet a further object is to incorporate a fault detection test facility in the transmitter that can detect errors either in the data input or in the internal circuitry of the device. These and other objects and advantages of the present invention will be apparent from the attached drawings and the Description of the Preferred Embodiments that follows.